EUV Lithography and Patterning Co-Optimization for Sub-3nm Era

The semiconductor industry has utilized device scaling to achieve cost reduction and performance enhancement from technology node to technology node in the past few decades. The introduction of Extreme Ultraviolet Lithography (EUVL) and patterning into high-volume manufacturing enabled the continuation of device scaling into the sub-3nm era, but also magnified the fabrication cost. At the sub-3nm node, the complexity of the device architecture and the aggressive size shrinkage have led numerous patterning challenges that are associated with the defectivity process window and electrical yield performance. These challenges include the pattern variation control, layer-to-layer placement error, two-dimensional print and pattern transfer limitations, and lithography stochastic effects. Specifically, with respect to the lithography stochastic effect, the combination of photon shot noise and material inhomogeneity can be attributed to the randomness of the image formation and the pattern variation. Besides these challenges in the current generation EUVL (NA 0.33) system, the industry has aimed to extend the image resolution to a sub-20nm pitch for the next-generation EUVL system, called high-NA (NA 0.55) EUVL. By increasing the numerical aperture (NA) in the system, the increasing intensity of light benefits image resolution, but also leads to the requirements of a narrow depth of focus (DOF) window and ultra-thin photoresist.

In this presentation, we review the fundamental bottlenecks of EUVL and patterning techniques for advanced node device fabrication. A detailed comparison between EUV single litho-etch (LE) and EUV double patterning (DP) reveals the optimum patterning method for the considerations of the single-layer physical performance, manufacturing readiness, and economics. In addition, the insertion of design technology co-optimization (DTCO) in the patterning process becomes a critical role to broaden the defectivity window and improve device performance. The co-optimization between the EUVL and patterning process is needed to achieve a successful patterning strategy for the sub-3nm node.