HPC Packaging: Heterogeneous IC Packages and a New Value Proposition

Today, cutting edge CMOS foundries are developing and shipping integrated circuits (ICs) with an astounding level of transistor density and product performance. Also, ever-present is the economic balancing act that integrated device manufacturers (IDMs) must make to establish a product performance and cost ratio that is a market winner. Single die, system on chip (SoC) integration has been the stalwart of the industry for the last 20 years. High costs to develop a new IC and functional block differentiation inside of a single die are beginning to move the industry to a better approach for staying on the cutting edge of high performance and at the same time, the lowest cost for products, whether they are in data centers, personal computers or smart phones.

The high value and high cost of cutting-edge CMOS silicon nodes is requiring rethinking about where to apply the latest transistors and which functional blocks operate just fine with older (N-1 or N-2) nodes. To realize products where this is possible requires a physical separation of these functions into discrete die, not just a logical segmentation as a Hardware Description Language (HDL). This approach has been a multi-year trend led by AMD and other Tier1 IDMs, whereby the physical architecture of the product is part of enabling a new level of product performance at a given cost point. This Heterogeneous Integration (HI) is performed at the package-level. Instead of super-integrations into one larger die, the integration of smaller, higher-yielding discrete die (chiplets) at the package level is used to form the fully functional product. With this design technique, product performance and total cost are optimized. There are different commercially viable approaches to achieve this package-level integration. Amkor has developed several key packaging technologies that permit multiple chiplets to be integrated into a single product package. These end products include high-density, multi-die MCMs which use a conventional IC package substrate and Flip Chip ball grid array (FCBGA) packages, but increasingly being driven to higher die-die density rules. Additionally, 2.5D Through Silicon Via (TSV) and High-Density Fan-Out (HDFO) offerings may be required, providing fine-line routing down to 2 µm line and 2 µm space with two-to-six-layer constructions. The future of these packaging technologies is bright. New product designs in this packaging class have increased 4-fold over the previous year. The silicon architectural flexibility, intellectual property (IP) reuse, time-to-market and lower overall cost continue to drive this innovation. As product design starts in these new technologies increase, a methodical approach for package reliability qualifications and mature design environments will be a key requirement now and in the future.

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