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Real-Time Sepsis Prediction Using Fusion of On-Chip Analog Classifier and Electronic Medical Record

3:35 pm - 3:55 pm

Sepsis is a leading cause of death worldwide, and 80% of patients have sepsis onset outside hospital settings. Real-time, at-home health monitoring for at-risk patients is a potential solution for predicting sepsis onset and providing timely intervention. This abstract presents a fusion AI framework that combines prediction scores from ECG signal and electronic medical record (EMR) for automating personalized sepsis detection 4 hours before onset.

The proposed framework has 3 components:

1) Analog on-chip machine-learning classifier that analyzes continuous ECG signal and predicts risk of sepsis

2) Random forest classifier based EMR model that predicts sepsis risk from demographics (age, gender, race, and ethnicity) and co-morbidity data

3) A meta-classifier that combines prediction scores from an on-chip classifier and EMR model for the prediction of sepsis onset.

The demographics data is encoded as an array of categorical variables, and normalized to [-1,1]. Patient co-morbidity data is collected in the form of the international classification of diseases (ICD-10) format which is then converted into a normalized score between [-1,1] using term frequency-inverse document frequency (tf-idf) statistics. The EMR model uses the normalized, encoded demographics and co-morbidity scores as features for sepsis prediction.

We have developed a mobile application that allows users to input their demographic and co-morbidity information, and predicts the risk of sepsis onset. The on-chip classifier can be embedded into a wearable sensor and improves the security of patient data by only transmitting prediction scores to the off-chip AI models. The proposed fusion framework is demonstrated on patient data collected from Emory University Hospital over 2014-2018. It is challenging to design on-chip AI for resource-constrained wearables since AI models are computationally intensive. Analog compute-in-memory (CIM) and reduced precision computations have been used for breaking von-neumann bottleneck and improving energy efficiency of AI circuits. However, state-of-the-art works have only demonstrated CIM macros, and not an integrated, multi-layer AI circuit. We have developed a fully integrated, 3-layer artificial neural network (ANN) for predicting sepsis from ECG sensor signals.

The ANN uses switched-capacitor (SC) CIM followed by analog activation circuits which remove ADCs that are a major bottleneck for CIM designs. Compared to SRAM-CIM, SC-CIM computes vector-matrix multiplications with higher linearity at the cost of reconfigurability of on-chip AI model weights. The ANN is fabricated in 65nm CMOS process and has a core area of 1.67mm2. The on-chip ANN detects sepsis with 85% accuracy from only ECG signal 4 hours before onset, while the accuracy improves to 91% after fusion with demographics and co-morbidity data. Linear support vector machine (SVM) is used as a meta-classifier for fusion. The complete on-chip AI circuit has an estimated energy consumption of 12.9nJ/inference.

The proposed classifier achieves 4x lower energy than state-of-the-art machine learning ASICs for different biomedical applications thanks to the analog implementation of the ANN. The proposed fusion framework achieves the highest accuracy while using a single modality sensor data source and no laboratory test results, which demonstrates the feasibility of the proposed technique for at-home monitoring and is a key differentiation from state-of-the-art.

Featured Speakers

Arindam Sanyal

Arindam Sanyal

Assistant Professor Arizona State University

 

Dr. Arindam Sanyal is an Assistant Professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University. Prior to this, he was an Assistant Professor in the Electrical Engineering Department at University at Buffalo. His research interests include analog/mixed signal design, bio-medical sensor design, analog security, and neuromorphic computing. He received his Ph.D. from The University of Texas at Austin in 2016. He serves as an Associate Editor in IET Electronics Letters, and a member of Analog Signal Processing Technical Committee (ASP-TC), and VLSI Systems and Applications Technical Committee (VSA-TC) within IEEE Circuits and Systems society.