Lithography/Patterning Strategies for an Industry in Flux
Thursday, December 9 | 10:30 am - 12:30 pm
TechTALKS Stage
EUVL is increasingly being used for high-volume manufacturing (HVM) by manufacturers of logic ICs and foundries, while memory manufacturers are working to insert it into the HVM of DRAM. Much effort is also being put into developing high-NA EUV exposure tools to enable the industry to extend Moore’s law for a number of years to come. As always, development activities must always take into account cost-effectiveness and other patterning strategies may be useful. This session will provide an update on the status of EUVL (including the EUV ecosystem) for HVM, other cost-effective patterning strategies, and the R&D activities needed to pursue them.
Agenda
EUV for Manufacturing for (at least) The Next Decade
Mike Lercel, PhD
ASML
10:35 am - 10:55 am
Laying the Groundwork for High NA EUV Patterning
Patrick Naulleau, PhD
Lawrence Berkeley National Lab
10:55 am - 11:15 am
EUV Lithography and Patterning Co-Optimization for Sub-3nm Era
Eric Liu
TEL Technology Center, America
11:15 am - 11:35 am
Dry Resist Technology for Improved EUV Patterning
Durga Singhal
Lam Research
11:35 am - 11:55 am
EUV Print Check with Broadband Plasma Wafer Inspection
Vidyasagar Anantha
KLA
11:55 am - 12:15 pm